/**
 * @file    gt9881_iwdt.h
 * @author  Giantec-Semi ATE
 * @brief   CMSIS GT98xx Device Peripheral Access Layer Header File
 * @version 0.1
 * 
 * @copyright Copyright (c) 2021 Giantec-Semi
 * 
 */

#ifndef GT98XX_DEVICE_GT9881_IWDT_H_
#define GT98XX_DEVICE_GT9881_IWDT_H_

#ifdef __cplusplus
  extern "C" {
#endif /* __cplusplus */

#include "gt9881.h"

/**
 * @addtogroup Peripheral_Registers_Structures
 * @{
 */
/**
 * @struct IwdtTypedef
 * @brief Idenpendent Watch-Dog Timer registers structure definition
 */
typedef struct tagIwdtTypedef {
  __IO uint32_t LDR;      ///< Watch-Dog Timer Load Register
  __IO uint32_t CRR;      ///< Watch-Dog Timer Counter Restart Register
  __IO uint32_t TCR;      ///< Watch-Dog Timer Control Register
  __IO uint32_t PLR;      ///< Watch-Dog Timer Reset Pulse Length Register
  __IO uint32_t CNT;      ///< Watch-Dog Timer Counter Register
  __IO uint32_t ISR;      ///< Watch-Dog Timer Interrupt Status Register
} IwdtTypedef;
/** @} Peripheral_Registers_Structures */

/**
 * @addtogroup Peripheral_Memory_Map
 * @{
 */
#define IWDT_BASE         (PERIPH_BASE + 0x9000UL)      ///< IWDT base address
/** @} Peripheral_Memory_Map */

/**
 * @addtogroup Peripheral_Declaration
 * @{
 */
#define IWDT              ((IwdtTypedef*)IWDT_BASE)     ///< IWDT operator
/** @} Peripheral_Declaration */

/**
 * @defgroup IWDT_Bitmap IWDT Bitmap 
 * @ingroup  Peripheral_Registers_Bits_Definition
 * @brief    Bitmap of Watch-Dog Timer Registers
 * @{
 */

#define IWDT_LDR_LOAD_VALUE_Pos         (0U)    ///< Position of IWDT_LDR_LOAD_VALUE
#define IWDT_LDR_LOAD_VALUE_Msk         (0xFFFFUL << IWDT_LDR_LOAD_VALUE_Pos)   ///< Bitmask of IWDT_LDR_LOAD_VALUE
/**
 * @def   IWDT_LDR_LOAD_VALUE
 * @brief Watchdog Timer load value
 * @note  Only write 0x76 to IWDT_CRR, the Load value can restart the counter values
 */
#define IWDT_LDR_LOAD_VALUE                             IWDT_LDR_LOAD_VALUE_Msk

#define IWDT_CRR_COUNTER_RES_Pos        (0U)    ///< Position of IWDT_CRR_COUNTER_RES
#define IWDT_CRR_COUNTER_RES_Msk        (0xFFUL << IWDT_CRR_COUNTER_RES_Pos)    ///< Bitmask of IWDT_CRR_COUNTER_RES
/**
 * @def   IWDT_CRR_COUNTER_RES
 * @brief Restart the WDT counter
 * @note  Only write 0x76 to IWDT_CRR, the LDR value can be load to Restart counter
 */
#define IWDT_CRR_COUNTER_RES            IWDT_CRR_COUNTER_RES_Msk

#define IWDT_TCR_TIMEOUT_RANGE_Pos      (10U)   ///< Position of IWDT_TCR_TIMEOUT_RANGE
#define IWDT_TCR_TIMEOUT_RANGE_Msk      (0x7UL << IWDT_TCR_TIMEOUT_RANGE_Pos)   ///< Bitmask of IWDT_TCR_TIMEOUT_RANGE
/**
 * @def   IWDT_TCR_TIMEOUT_RANGE
 * @brief When a WDT Interrupt is generated, if it is not cleared before the Time-out time, then it generates a system reset.
 * <pre>
 * @a 3'b000 : 16 of WDT Counter clock cycles
 * @a 3'b001 : 32 of WDT Counter clock cycles
 * @a 3'b010 : 64 of WDT Counter clock cycles
 * @a 3'b011 : 128 of WDT Counter clock cycles
 * @a 3'b100 : 256 of WDT Counter clock cycles
 * @a 3'b101 : 512 of WDT Counter clock cycles
 * @a 3'b110 : 1K of WDT Counter clock cycles
 * @a 3'b111 : Reserved
 * </pre>
 */
#define IWDT_TCR_TIMEOUT_RANGE          IWDT_TCR_TIMEOUT_RANGE_Msk

#define IWDT_TCR_ENABLE_Pos             (9U)    ///< Position of IWDT_TCR_ENABLE
#define IWDT_TCR_ENABLE_Msk             (0x1UL << IWDT_TCR_ENABLE_Pos)    ///< Bitmask of IWDT_TCR_ENABLE
/**
 * @def   IWDT_TCR_ENABLE
 * @brief IWDT enable
 * <pre>
 * @a 1'b0 : Timer is disabled(count value is set to FFFF_FFFFh)
 * @a 1'b1 : Timer is enabled
 * </pre>
 */
#define IWDT_TCR_ENABLE                 IWDT_TCR_ENABLE_Msk

#define IWDT_TCR_ACTION_Pos             (8U)    ///< Position of IWDT_TCR_ACTION
#define IWDT_TCR_ACTION_Msk             (0x1UL << IWDT_TCR_ACTION_Pos)    ///< Bitmask of IWDT_TCR_ACTION
/**
 * @def   IWDT_TCR_ACTION
 * @brief IWDT action
 * <pre>
 * @a 1'b0 : When the timer count reaches zero, a reset output is generated.
 * @a 1'b1 : When the timer count reaches zero, an interrupt request is generated.
 * </pre>
 */
#define IWDT_TCR_ACTION                 IWDT_TCR_ACTION_Msk

#define IWDT_TCR_DIVISOR_Pos            (0U)    ///< Position of IWDT_TCR_DIVISOR
#define IWDT_TCR_DIVISOR_Msk            (0x7UL << IWDT_TCR_DIVISOR_Pos)   ///< Bitmask of IWDT_TCR_DIVISOR
/**
 * @def   IWDT_TCR_DIVISOR
 * @brief The 3 bits divide the system clock by following prescale divisors.
 * <pre>
 * @a 4'b0000 : Divide by 2
 * @a 4'b0001 : Divide by 4
 * @a 4'b0010 : Divide by 8
 * @a 4'b0011 : Divide by 16
 * @a 4'b0100 : Divide by 32
 * @a 4'b0101 : Divide by 64
 * @a 4'b0110 : Divide by 128
 * @a 4'b0111 : Divide by 256
 * </pre>
 */
#define IWDT_TCR_DIVISOR                IWDT_TCR_DIVISOR_Msk

#define IWDT_CNT_COUNTER_VAL_Pos        (0U)    ///< Position of IWDT_CNT_COUNTER_VAL
#define IWDT_CNT_COUNTER_VAL_Msk        (0xFFFFUL << IWDT_CNT_COUNTER_VAL_Pos)    ///< Bitmask of IWDT_CNT_COUNTER_VAL
/**
 * @def   IWDT_CNT_COUNTER_VAL
 * @brief Current value of the timer counter
 */
#define IWDT_CNT_COUNTER_VAL            IWDT_CNT_COUNTER_VAL_Msk

#define IWDT_ISR_INTSTAT_Pos            (0U)    ///< Position of IWDT_ISR_INTSTAT
#define IWDT_ISR_INTSTAT_Msk            (0x1UL << IWDT_ISR_INTSTAT_Pos)   ///< Bitmask of IWDT_ISR_INTSTAT
/**
 * @def   IWDT_ISR_INTSTAT
 * @brief This register shows the interrupt status of the WDT.
 * <pre>
 * @a 1'b1 : Interrupt is active
 * @a 1'b0 : Interrupt is inactive
 * When this register is written 1, the WDT interrupt is cleared to 0 without restarting the watchdog counter.
 * </pre>
 */
#define IWDT_ISR_INTSTAT                IWDT_ISR_INTSTAT_Msk

/** @} IWDT_Bitmap */

/**
 * @addtogroup Exported_Macros
 * @{
 */

/**
 * @def IS_IWDT_INSTANCE
 * @brief Check if INSTANCE is IWDT instance
 */
#define IS_IWDT_INSTANCE(INSTANCE)              ((INSTANCE) == IWDT)

/**
 * @def IWDT_CNT_RESTART_VALUE
 * @brief Write to IWDT_CRR to load LDR value to Restart counter
 */
#define IWDT_CNT_RESTART_VALUE                  (0x76U)

/** @} Exported_Macros */

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* GT98XX_DEVICE_GT9881_IWDT_H_ */
